The present invention relates to the field of high-speed networks, and more particularly to interconnected networks constituted by high-speed serial links connecting nodes of data processing systems or data communication systems, hereinafter called modules.
Hereinafter, and in general, the connection of two modules that are remote from one another is called a linkage or link.
The invention is described below based on the protocol SDH, the abbreviation for Synchronous Digital Hierarchy, defined by the ITU, the abbreviation for xe2x80x9cInternational Telecommunication Union,xe2x80x9d in its G.708, G.709 and G.783 guidelines.
However, the invention is not limited to the utilization of this protocol, which is given as an example to provide a good understanding of the invention.
The increase in the demand for multimedia services, particularly the transmission of digitized images, and the specialized interconnections of local area networks comprising an increasing number of processors interconnected with one another, require higher and higher speeds under strict limitations in terms of cost, transmission time, space and the integrity of the transmitted information.
The high-speed serial links of the prior art, particularly the serial links of the SDH type that use a link constituted by two opposite one-way point-to-point links, are no longer able to meet the demand for speeds that can exceed several tens of GB/s, typically exceeding or equalling 50 GB/s. Such speeds are reached especially when a large number of processors are communicating with one another in a data processing machine or a network connecting several machines to one another.
The limitation due to the maximum allowable speed affects the latency of a data processing machine, which is an important parameter to consider in the efficiency of a multi-module machine, especially when the distance between the modules is large and/or when the number of processors communicating with one another is large.
One solution for solving this problem consists of parallelizing several point-to-point links.
One particular solution of this type is known from the document entitled xe2x80x9cHigh Performance Parallel Interface-Mechanical, Electrical and Signalling Protocol Specification (HPPI-PH),xe2x80x9d published in xe2x80x9cX3T11 Maintenance Copy of American National Standard X3.183-1991.xe2x80x9d This document describes a parallel point-to-point interface for transmitting digital data at speeds of 800 or 1600 Mb/s between data processing machines, which data is conveyed through twisted pairs of copper wires over distances of more than 25 m.
However, this solution runs into the major problem of the deviation of the propagation times in the parallel links, also known as xe2x80x9cskew,xe2x80x9d which makes it necessary to solve the problem of resynchronizing the data conveyed through each line on reception.
This problem is even more difficult to solve when the operating frequency of the modules is high.
In fact, at frequencies higher than 200 MHz, for which the skews become greater than the bit period, the static deviations are substantial, and in complex configurations the sum of the contributions of the skews for a 10-meter link can reach 10 ns. For a 10-meter link, there is typically a maximum of 4 ns in the cables and two times 3 ns in the transceivers.
If the information contained in the messages to be transmitted through a given number of links is distributed at a rate of 1 bit per link, the deviations cause the information to arrive at the ends of the links at different instants. The problem is that for a frequency of 200 MHz, or 5 ns after the departure of the information, the bits arrive in the wrong order, and is no longer known which message the bits received at the end of the link belong to.
The object of the invention is specifically to eliminate these drawbacks.
Another object of the present invention is to offer a physical interface structure capable of supporting speeds of several GB/s, typically greater than or equal to 5 GB/s, through 16 channels, or 2.5 Gb/s per channel, in cables having a skew on the order of xc2x14 ns.
Hereinafter, the term xe2x80x9cchannelxe2x80x9d will be used to define the level of parallelization of a link and the term xe2x80x9ccablexe2x80x9d will be used to define the physical medium of the links.
Likewise, the unit GB/s means gigabytes per second and the unit Gb/s means gigabits per second: a byte corresponds to an octet, or 8 bits.
The skew of xc2x14 ns, which corresponds to a length of several meters, should be compared to a bit period, typically on the order of 0.4 ns, and a frame header, on the order of 50 ns.
The bit period therefore has a lower order of magnitude than the skew, while the duration of the header has a higher order of magnitude than the skew. It is known to increase the bit period by increasing the number of parallelized channels, but the number of physical connection points must remain compatible with the dimensions of a mass-produced card.
For this reason, the first subject of the invention is a process for interconnection between data processing or data communication modules by means of high-speed point-to-point serial links conveying multiplexed information, organized into frames and comprising a start-of-frame recognition pattern, of the type consisting of parallelizing several high-speed channels, making it possible to increase the flow of information exchanged between the modules.
The process according to the invention is characterized in that it consists, on transmission and on reception, of performing an analog synchronization of the basic clocks of each module to a reference clock generated by a module designated among the modules as a reference module, called the master module, the other modules being called slave modules, and of digitally synchronizing the start-of-frame of each slave module to the start-of frame sent by the master module.
According to one characteristic, for the analog synchronization on transmission, the process consists of:
extracting the basic clock signals of each slave module from the signals conveyed through each of the respective links connecting the master module to the slave modules;
frequency-locking and phase-locking each slave module to the data of one channel, chosen as the master channel, coming from the master module; and
from the basic clock signals, generating in each slave module a new clock signal with a given frequency higher than its own clock frequency, conveyed by the link connecting the slave module to the master module, and with a cycle imposed by the clock of the master module.
According to another characteristic, for the digital synchronization on transmission, it consists of:
detecting the start-of-frame conveyed through each link;
digitally aligning the start-of-frame of each channel with the start-of-frame pattern sent by the master module.
According to another characteristic, for the analog synchronization on reception, it consists of:
designating a master channel among all of the channels forming the link connecting each slave module to the, master module;
from the data conveyed through the master channel, extracting the clock signal sent by the module connected to the link; and
generating a clock signal with a frequency higher than the frequency of the extracted clock signal, to be used as a sampling frequency for the respective data signals extracted from the other links.
According to another characteristic, for the digital synchronization on reception, it consists of digitally aligning, to the nearest bit, all of the starts-of-frame of the links with the starts-of frame of the master link, at a given frequency corresponding to the throughput of the data conveyed through each of the links.
According to another characteristic, there is an overlap of all the headers related to each link.
Another subject of the present invention is an interconnection interface for implementing the above process.
The interface is characterized in that it comprises, in each module:
multiplexing means associated with each serial link, disposed in the physical layer of the module, making it possible to distribute the data transmitted through the global link at a speed determined by the sending module to a given number of parallel links, each parallel link conveying part of the data at a speed higher than the speed of the data blocks sent by the sending module; and
means for demultiplexing the given number of parallel links respectively conveying the data parts received, in order to reconstitute the data that has passed through the interconnection interface, synchronously and with integrity, at a speed corresponding to the speed allowable by the receiving module.
According to another characteristic, the multiplexing/demultiplexing means comprise a sending block and a receiving block, the sending block comprising a plurality of clock generating blocks and the receiving block comprising a plurality of clock retrieving blocks, each generating block using the sending logic for a given link to which it is connected, the sending block synchronizing the plurality of generating blocks, and each retrieving block using receiving means for a given link, the receiving block defining the clock domain related to the reception of the given number of links connected to the same module.
According to another characteristic, each clock retrieving block comprises:
a logical circuit that senses the leading edges of the data signal conveyed through the link to which it is connected, making it possible to extract a pure and substantially fixed clock frequency from the data transmitted through the link; and
a phase-locked oscillator that receives the clock frequency output by the logical circuit.
According to another characteristic, the receiving blocks include a device for correcting the deviation of the propagation times in the parallel links, also called the skew.
According to another characteristic, the skew correcting device comprises:
means for generating a local receiving clock from the signal received from the master link;
means for phase-shifting the signals received from the slave links;
means for sampling the phase-shifted signals at a rate imposed by the local receiving clock;
means for phase-shifting the sampled signals in the signal received from the slave link, the logical contents of the phase-shifted signals corresponding to a bit shift defined by a given whole number of periods STM-N, where N corresponds to the level of interleaving; and
means defining a window for operating the phase-shifting means specific to each slave link, the phase-shifting means being active in the phase preceding the detection of the start bit and inactive during the transfer of the rest of the frame.
The digital synchronization of the frames is achieved through a digital alignment of the recognition patterns, hereinafter called xe2x80x9cstart bits,xe2x80x9d contained in the starts-of-frame provided according to the SDH data transport protocol.
The present invention uses the detection of each start-of-frame and the periodicity of these frames to perform a precise logical synchronization of the information transported by the frames.
One advantage of the present invention is that it specifically separates the logical transport layers from the physical layers for access to the media.